FPGA-Based Wireless Sensor Node Architecture for High Performance Applications

While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements

Wireless Sensor Network Application for Environmental Impact Analysis and Control

Traditional Wireless Sensor Networks (WSNs) applications take advantage of the new low cost low power consuming integrated sensors that appear with the evolution of Micro Electromechanical Systems (MEMS). This kind of sensors is suitable for WSNs, due to the reduced size, their interfaces and their low power consumption. However, during the last years, WSNs have found new niches of application where such sensors are not usable, due to the nature of the parameter to be measured. In these scenarios, new approaches must be taken in order to satisfy the requirements. But new problems appear, like cost and size increase. In this paper, an application where parameters like gas concentration, conductivity or pH have to be measured in a coffee factory is presented. The drawbacks of such a solution are highlighted, and the solution in the field of the wireless sensor networks adopted is detailed

Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs

ARTICo3 is an architecture that permits to dynamically set an arbitrary number of reconfigurable hardware accelerators, each containing a given number of threads fixed at design time according to High Level Synthesis constraints. However, the replication of these modules can be decided at runtime to accelerate kernels by increasing the overall number of threads, add modular redundancy to increase fault tolerance, or any combination of the previous. An execution scheduler is used at kernel invocation to deliver the appropriate data transfers, optimizing memory transactions, and sequencing or parallelizing execution according to the configuration specified by the resource manager of the architecture. The model of computation is compatible with the OpenCL kernel execution model, and memory transfers and architecture are arranged to match the same optimization criteria as for kernel execution in GPU architectures but, differently to other approaches, with dynamic hardware execution support. In this paper, a novel design methodology for multithreaded hardware accelerators is presented. The proposed framework provides OpenCL compatibility by implementing a memory model based on shared memory between host and compute device, which removes the overhead imposed by data transferences at global memory level, and local memories inside each accelerator, i.e. compute unit, which are connected to global memory through optimized DMA links. These local memories provide unified access, i.e. a continuous memory map, from the host side, but are divided in a configurable number of independent banks (to increase available ports) from the processing elements side to fully exploit data-level parallelism. Experimental results show OpenCL model compliance using multithreaded hardware accelerators and enhanced dynamic adaptation capabilities

Wireless Sensor Network Solution for Sustainable Food Production

Environmental monitoring has become a key aspect in food production over the last few years. Due to their low cost, low power consumption and flexibility, Wireless Sensor Networks (WSNs) have turned up as a very convenient tool to be used in these environments where no intrusion is a must. In this work, a WSN application in a food factory is presented. The paper gives an overview of the system set up, covering from the initial study of the parameters and sensors, to the hardware-software design and development needed for the final tests in the factory facilities

Power-Aware Multi-Objective Evolvable Hardware System on an FPGA

Dynamic and Partial Reconfiguration (DPR) allows a system to be able to modify certain parts of itself during run-time. This feature gives rise to the capability of evolution: changing parts of the configuration according to the online evaluation of performance or other parameters. The evolution is achieved through a bio-inspired model in which the features of the system are identified as genes. The objective of the evolution may not be a single one; in this work, power consumption is taken into consideration, together with the quality of filtering, as the measure of performance, of a noisy image. Pareto optimality is applied to the evolutionary process, in order to find a representative set of optimal solutions as for performance and power consumption. The main contributions of this paper are: implementing an evolvable system on a low-power Spartan-6 FPGA included in a Wireless Sensor Network node and, by enabling the availability of a real measure of power consumption at run-time, achieving the capability of multi-objective evolution, that yields different optimal configurations, among which the selected one will depend on the relative “weights” of performance and power consumption

Análisis dinámico de la suspensión Pull Rod y Push Rod para el vehículo eléctrico tipo monoplaza

SENA was proposed as a challenge to design and build an electric vehicle type formula for competitions nationwide. The subject matter of this article is to perform dynamic analysis Pull-Rod and Push-Pull the car suspension for optimum relationship between stability, weight and strength, seeking to improve performance race car. Another important aspect of the system is driver safety, a fault in this system may lead to loss of limb or life

Análisis dinámico de la suspensión Pull-Rod y PuhsRod para el vehículo eléctrico tipo monoplaza

SENA was proposed as a challenge to design and build an electric vehicle type formula for competitions nationwide. The subject matter of this article is to perform dynamic analysis Pull-Rod and Push-Pull the car suspension for optimum relationship between stability, weight and strength, seeking to improve performance race car.The structure needs the finite element method for analysis, which involves the use of CAE tools to verify the results. In this case, the study will be conducted by software Solidworks. The dynamic analysis, test track for suspension behavior, the behavior of the spring-damper is stabilized by the Matlab software.El SENA se propuso el reto de diseñar y construir un vehículo eléctrico tipo fórmula para competiciones a nivel nacional, por lo que el objetivo de este artículo fue realizar un análisis dinámico de la suspensión Pull- Rod y Push- Rod para el vehículo con una relación óptima entre estabilidad, peso y fuerza, con el fin de mejorar el rendimiento del vehículo de carreras.La estructura necesitó del método de los elementos finitos para su análisis, lo que conllevó a la utilización de herramientas CAE para verificar los resultados. En este caso, el estudio se realizó mediante el software Solidworks. Para el análisis dinámico, las pruebas se realizaron en pista para el comportamiento de la suspensión, y el comportamiento del resorte -amortiguador se estabilizó mediante el software Matlab

Power management techniques in an FPGA-Based WSN node for high performance application

In this work, the power management techniques implemented in a high-performance node for Wireless Sensor Networks (WSN) based on a RAM-based FPGA are presented. This new node custom architecture is intended for high-end WSN applications that include complex sensor management like video cameras, high compute demanding tasks such as image encoding or robust encryption, and/or higher data bandwidth needs. In the case of these complex processing tasks, yet maintaining low power design requirements, it can be shown that the combination of different techniques such as extensive HW algorithm mapping, smart management of power islands to selectively switch on and off components, smart and low-energy partial reconfiguration, an adequate set of save energy modes and wake up options, all combined, may yield energy results that may compete and improve energy usage of typical low power microcontrollers used in many WSN node architectures. Actually, results show that higher complexity tasks are in favor of HW based platforms, while the flexibility achieved by dynamic and partial reconfiguration techniques could be comparable to SW based solutions

Live Demonstration: A Dynamically Adaptable Image Processing Application Running in an FPGA-Based WSN Platform

This 1-Page Demonstration paper is included in the track “Multimedia Systems and Applications”. The work has been already published in [1] and [2]. The main idea of the demonstration is to show how the Virtual Architecture ARTICo3 works within a high performance wireless sensor node called HiReCookie. The selected demo includes an image processing application with several filters running as different kernels within the architecture ARTICo3. The virtual architecture works in a Spartan-6 FPGA included in the HiReCookie Node, [3] and [4]. During the demonstration, an image taken from a video camera attached to the node will be processed in real time by several dynamically reconfigurable kernels (median filters and edge detectors) under different working conditions. The solution scope includes solutions trading off among Low Power, Dependability and High Performance Computing

Execution modeling in self-aware FPGA-based architectures for efficient resource management

SRAM-based FPGAs have significantly improved their performance and size with the use of newer and ultra-deep-submicron technologies, even though power consumption, together with a time-consuming initial configuration process, are still major concerns when targeting energy-efficient solutions. System self-awareness enables the use of strategies to enhance system performance and power optimization taking into account run-time metrics. This is of particular importance when dealing with reconfigurable systems that may make use of such information for efficient resource management, such as in the case of the ARTICo3 architecture, which fosters dynamic execution of kernels formed by multiple blocks of threads allocated in a variable number of hardware accelerators, combined with module redundancy for fault tolerance and other dependability enhancements, e.g. side-channel-attack protection. In this paper, a model for efficient dynamic resource management focused on both power consumption and execution times in the ARTICo3 architecture is proposed. The approach enables the characterization of kernel execution by using the model, providing additional decision criteria based on energy efficiency, so that resource allocation and scheduling policies may adapt to changing conditions. Two different platforms have been used to validate the proposal and show the generalization of the model: a high-performance wireless sensor node based on a Spartan-6 and a standard off-the-shelf development board based on a Kintex-7